Author Archives: Konstantin S. Solnushkin

Fat-tree and Torus Articles Now Available at arXiv.org

In case you wanted something more than an informal introduction into the world of fat-tree and torus networks — here you are. A formal problem statement (and solution!) in an academic form is given in these two articles hosted at … Continue reading

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Cluster Design Tools Updated (ver. 0.8.1a)

A new version of Cluster Design Tools was made available for download today. The change concerns the UPS sizing algorithm, making it yet more optimal.      

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Real Cost Comparison of Fat-tree and Torus Networks

Thanks to Mellanox Technologies, our tool that designs fat-tree and torus networks now operates with real life prices for InfiniBand hardware. Mellanox kindly provided list prices for the previous generation of switches, InfiniBand QDR: these figures are not likely to … Continue reading

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Latency Everywhere

People from the high-performance computing field have a clear understanding that performance of technical systems (of various nature) is characterized by two metrics: throughput and latency. People in other fields sometimes focus on either throughput or latency alone. For many … Continue reading

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“I’ll Start My Own Supercomputer Conference”

Remember that moment from Futurama when Robot Bender promises to set up his own theme park? Forget about the theme park, because is seems that we now have several supercomputer conferences. Why? And does it do us any good? I … Continue reading

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Finally, A Topology-Aware MPI Implementation

Good news from the Supercomputing-2012 (SC12) conference: ten collaborators (including a talented team led by Dr. Dhabaleswar K. Panda) presented a paper on a new approach for assigning processes to compute nodes in InfiniBand networks. Roughly, it works as follows: … Continue reading

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How To Size Your UPS System: More Power, Igor!

We now have a tool to size UPS systems! Find it in the menu above, or use this link. (As for the headline, Igor is a character of Tom Holt’s novel, “Igor”)

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System-on-Wafer: Integrated Circuit Packaging Considered Harmful

Silicon wafers contain enormous numbers of microprocessors. For example, a typical 300 mm wafer, as used by Intel, can contain about 130 dies of Intel Core i7 “Sandy Bridge-E” CPUs (use the formula, Luke, and substitute S=435 mm² for a … Continue reading

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Torus Network: As Round As It Gets

Fat-trees have great performance characteristics, but they can be costly for some installations. Blocking fat-trees can be used as an alternative, but if your computational task has locality of communications and is well suited to torus networks — why not … Continue reading

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Fruits of Computing: Redefining “Green” in HPC Energy Usage

Suppose you are visiting a supercomputing centre for several days. Each day you submit your compute jobs and then go to a nearby tropical garden. While your jobs are being computed, you enjoy fresh tropical fruit, listen to exotic birds … Continue reading

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